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| [ak5701] 16-bit ? stereo adc with pll & mic- a mp ak5701 general description the ak5701 features a 16-bit ster eo adc. input circuits incl ude a microphone-amplifier and an alc (auto level control) circuit that is suitable for portable application wi th recording function. on-chip pll supports base-band clock of mobile phone, therefore it is easy to connect with dsp. the ak5701 is available in a 24pin qfn, utilizing less board space than com petitive offerings. features 1. resolution: 16bits 2. recording function - 2 stereo input selector - full-differential or single-ended input - mic amplifier (+30db/+15db or 0db) - input voltage: 1.8vpp@va=3.0v (= 0.6 x avdd) - adc performance: s/(n+d): 78d b, dr, s/n: 89db@mgain=0db s/(n+d): 77db, dr, s/n: 87db@mgain=+15db s/(n+d): 72db, dr, s/n: 77db@mgain=+30db - digital hpf for dc-offset cancellation (fc=3.4hz@fs=44.1khz) - digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) 3. sampling rate: - pll slave mode (exlrck pin): 7.35khz 48khz - pll slave mode (exbclk pin): 7.35khz 48khz - pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz - pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz - ext slave mode: 7.35khz 48khz (256fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 4. pll input clock: - mcki pin: 27mhz, 26mhz, 24mhz, 19.2mhz, 13. 5mhz, 13mhz, 12.288mhz, 12mhz, 11.2896mhz - exlrck pin: 1fs - exbclk pin: 32fs/64fs 5. master/slave mode 6. audio interface format: msb first, 2?s compliment - dsp mode, 16bit msb justified, i 2 s 7. p i/f: 3-wire serial 8. power supply: - avdd: 2.4 3.6v - dvdd: 1.6 3.6v 9. power supply current: 8ma 10. ak5701vn: ta = ? 30 85 c AK5701KN: ta = ? 40 85 c 11. package: 24pin qfn (4mm x 4mm) ms0404-e-02 2007/08 - 1 -
[ak5701] block diagram lin1 vcom avdd avss rin1 vcoc mcki sdto bclk lrck dvdd adc mix audio i/f controller pll pdn s e l mcko exlrck exbclk exsdti control register csn cclk cdti s e l lin2 rin2 alc or ivol mpwr dvss csp hpf figure 1. block diagram ms0404-e-02 2007/08 - 2 - [ak5701] ordering guide ak5701vn 30 a +85 q c 24pin qfn (0.5mm pitch) AK5701KN 40 a +85 q c 24pin qfn (0.5mm pitch) akd5701 evaluation board for ak5701 pin layout mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck ak5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 comparison with ak5355vn function ak5355vn ak5701 input selector no yes input gain +15db/0db +30db/+15db/0db mic bias no yes alc no yes mono mic mode no yes audio i/f format left justified, i 2 s dsp mode, left justified, i 2 s pll no yes master mode no yes output data selector no yes serial control no yes power supply 2.1 a 3.6v avdd=2.4 a 3.6v dvdd=1.6 a 3.6v package 20pin qfn (4.2mm x 4.2mm) 24pin qfn (4mm x 4mm) ambient temperature 40 a +85 q c ak5701vn : 30 a +85 q c AK5701KN : 40 a +85 q c ms0404-e-02 2007/08 - 3 - [ak5701] pin/function no. pin name i/o function 1 vcom o common voltage output pin, 0.5 x avdd bias voltage of adc inputs. 2 avss - analog ground pin 3 avdd - analog power supply pin 4 dvdd - digital power supply pin 5 dvss - digital ground pin 6 bclk o audio serial data clock pin 7 lrck o input / output channel clock pin 8 sdto o audio serial data output pin 9 csp i chip select polarity pin ?h?: csn pin = ?h? active, c1-0 = ?01? ?l?: csn pin = ?l? active, c1-0 = ?10? 10 mcko o master clock output pin 11 exsdti i external audio serial data input pin 12 exlrck i external input / output channel clock pin 13 exbclk i external audio serial data clock pin 14 mcki i external master clock input pin 15 cdti i control data input pin 16 cclk i control data clock pin (internal pull-down at csp pin = ?h?) 17 csn i chip select pin 18 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. 19 mpwr o mic power supply pin rin2 i rch analog input 2 pin (mdif2 bit = ?0?) 20 rin+ i rch positive input pin (mdif2 bit = ?1?) lin2 i lch analog input 2 pin (mdif2 bit = ?0?) 21 rin ? i rch negative input pin (mdif2 bit = ?1?) rin1 i rch analog input 1 pin (mdif1 bit = ?0?) 22 lin ? i lch negative input pin (mdif1 bit = ?1?) lin1 i lch analog input 1 pin (mdif1 bit = ?0?) 23 lin+ i lch positive input pin (mdif1 bit = ?1?) 24 vcoc o output pin for loop filter of pll circuit this pin should be connected to avss with one resistor and capacitor in series. note 1. all input pins except analog input pins (lin1, rin1, lin2, rin2) should not be left floating. v handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog mpwr, vcoc, lin1/lin+, rin1/lin ? , lin2/rin? , rin2/rin+ these pins should be open. bclk, lrck, sdto, mcko these pins should be open. digital mcki, exbclk, exlrck, exsdti these pins should be connected to dvss. ms0404-e-02 2007/08 - 4 - [ak5701] absolute maximum ratings (avss, dvss=0v; note 2 ) parameter symbol min max units power supplies: analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v |avss ? dvss| ( note 3 ) gnd - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 4 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 5 ) vind ? 0.3 dvdd+0.3 v ambient temperature ak5701vn ta ? 30 85 c (powered applied) AK5701KN ta ? 40 85 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground. note 3. avss and dvss must be connected to the same analog ground plane. note 4. lin1/lin+, rin1/lin ? , lin2/rin ? , rin2/rin+ pins note 5. pdn, csn, cclk, cdti, csp, mcki, exsdti, exlrck, exbclk pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (avss, dvss=0v; note 2 ) parameter symbol min typ max units power supplies analog avdd 2.4 3.0 3.6 v ( note 6 ) digital dvdd 1.6 3.0 avdd v note 2. all voltages with respect to ground. note 6. the power-up sequence between avdd and dvdd is not critical. when only avdd is powered off, the power supply current of dvdd at power-down mode may be increased. dvdd should not be powerd off while avdd is powered on. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. ms0404-e-02 2007/08 - 5 - [ak5701] analog characteristics (ta=25 c; avdd, dvdd=3.0v; avss=dvss=0v; pll master mode; mcki=12mhz, fs=44.0995khz, bclk=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: lin1, rin1, lin2, rin2 pins; mdif1 = mdif2 bits = ?0? (single-ended inputs) mgain1-0 bits = ?00? 40 60 80 k input resistance mgain1-0 bits = ?01? or ?10? 20 30 40 k mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - +15 - db gain mgain1-0 bits = ?10? - +30 - db mic amplifier: lin+, lin ? , rin+, rin ? pins; mdif1 = mdif2 bits = ?1? (full-differential input) input voltage ( note 7 ) mgain1-0 bits = ?01? - - 0.37 vpp mgain1-0 bits = ?10? - - 0.066 vpp mic power supply: mpwr pin output voltage ( note 8 ) 2.02 2.25 2.48 v load resistance 0.5 - - k load capacitance - - 30 pf adc analog input characteristics: lin1/rin1/lin2/rin2 pins (single-ended inputs) adc ivol, mgain=+15db, ivol=0db, alc=off resolution - - 16 bits mgain=+30db - 0.057 - vpp mgain=+15db 0.27 0.32 0.37 vpp input voltage ( note 9 ) mgain=0db 1.53 1.80 2.07 vpp 67 77 - db s/(n+d) (? 0.5dbfs) ( note 10 ) 79 87 - db d-range ( ? 60dbfs, a-weighted) ( note 11 ) s/n (a-weighted) ( note 11 ) 79 87 - db interchannel isolation ( note 12 ) 80 90 - db mgain=+30db - 0.2 - db mgain=+15db - 0.2 1.0 db interchannel gain mismatch mgain=0db - 0.2 0.5 db power supplies: power supply current: avdd+dvdd power up (pdn pin = ?h?) ( note 13 ) - 8 12 ma power down (pdn pin = ?l?) ( note 14 ) - 1 20 a note 7. the voltage difference between lin+/rin+ and lin ? /rin? pins. ac coupling capacitor should be connected in series at each input pin. fu ll-differential input is not available at m gain1-0 bits = ?00?. maximum input voltage of lin+, lin ? , rin+ and rin ? pins is proportional to avdd voltage, respectively. vin = |(l/rin+) ? (l/rin ? )| = 0.123 x avdd (max)@mgain1-0 bits = ?01?, 0.022 x avdd (max)@mgain1-0 bits = ?10?. when the signal larger than above value is input to lin+, lin ? , rin+ or rin? pin, adc does not operate normally. note 8. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ). note 9. input voltage is proportional to avdd voltage. vin = 0.107 x avdd (typ)@mgain1-0 bits = ?01? (+15db), vin = 0.6 x avdd(typ)@mgain1-0 bits = ?00? (0db). note 10. 80db(typ)@mgain=0db, 70db(typ)@mgain=+30db note 11. 89db(typ)@mgain=0db, 77db(typ)@mgain=+30db note 12. 100db(typ)@mgain=0db, 80db(typ)@mgain=+30db note 13. pll master mode (mcki=12mhz), pmadl = pm adr = pmvcm = pmpll = pmmp = m/s bits = ?1? and mcko bit = ?0?. mpwr pin outputs 0ma. avdd=6.4ma(typ), dvdd=1.6ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd=5.7ma(typ), dvdd=1.3ma(typ). bypass mode (thr bit = ?1?, pmadl = pmadr = m/s bits = ?0?), fs=8khz: avdd=1 a(typ), dvdd=150 a(typ). note 14. all digital input pins are fixed to dvdd or dvss. ms0404-e-02 2007/08 - 6 - [ak5701] filter characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v; fs=44.1khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 15 ) pb 0 - 17.4 khz 0.1db - 20.0 - khz ? 1.0db - 21.1 - khz ? 3.0db stopband ( note 15 ) sb 25.7 - - khz passband ripple pr - - db 0.1 stopband attenuation sa 65 - - db group delay ( note 16 ) gd - 18 - 1/fs group delay distortion - 0 - gd s adc digital filter (hpf): hpf1-0 bits = ?00? frequency response ( note 15 ) fr - 3.4 - hz ? 3.0db - 10 - hz ? 0.5db - 22 - hz ? 0.1db note 15. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.454*fs (@ ? 1.0db). each response refers to that of 1khz. note 16. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf. dc characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage except csp pin; 2.2v dvdd 3.6v vih 70 % dvdd - - v except csp pin; 1.6v dvdd <2.2v vih 80 % dvdd - - v csp pin vih 90% dvdd - - v low-level input voltage except csp pin; 2.2v dvdd 3.6v vil - - 30 % dvdd v except csp pin; 1.6v dvdd <2.2v vil - - 20 % dvdd v csp pin vil - - 10 % dvdd v high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (iout= 200 a) vol - - 0.2 v input leakage current ( note 17 ) iin - - 10 a note 17. when csp pin is ?h?, cclk pin has internal pull-down device, normally 100k . ms0404-e-02 2007/08 - 7 - [ak5701] ms0404-e-02 2007/08 - 8 - switching characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v; c l =20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency except dsp mode 1 fs 7.35 - 48 khz dsp mode 1 ( note 18 ) fsd 14.7 - 96 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1-0 bit = ?01? tbck - 1/(32fs) - ns bcko1-0 bit = ?10? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns pll slave mode (pll reference clock = exlrck pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns note 18. sampling frequency is 7.35khz 48khz. [ak5701] ms0404-e-02 2007/08 - 9 - parameter symbol min typ max units pll slave mode (pll reference clock = exbclk pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns exlrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1-0 bit = ?01? tbck - 1/(32fs) - ns bcko1-0 bit = ?10? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % [ak5701] parameter symbol min typ max units audio interface timing (dsp mode) master mode tdbf 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bclk ? ? ( note 19 ) 0.5 x tbck ? 40 tdbf 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bclk ? ? ( note 20 ) 0.5 x tbck ? 40 tbsd - 70 ns bclk ? ? to sdto (bckp bit = ?0?) ? 70 tbsd - 70 ns bclk ? ? to sdto (bckp bit = ?1?) ? 70 slave mode tlrb 0.4 x tbck - - ns exlrck ? ? to exbclk ? ? ( note 19 ) tlrb 0.4 x tbck - - ns exlrck ? ? to exbclk ? ? ( note 20 ) tblr 0.4 x tbck - - ns exbclk ? ? to exlrck ? ? ( note 19 ) tblr 0.4 x tbck - - ns exbclk ? ? to exlrck ? ? ( note 20 ) tbsd - - 80 ns exbclk ? ? to sdto (bckp bit = ?0?) tbsd - - 80 ns exbclk ? ? to sdto (bckp bit = ?1?) audio interface timing (left justified & i 2 s) master mode tmblr - 40 ns bclk ? ? to lrck edge ( note 21 ) ? 40 tlrd lrck edge to sdto (msb) - 70 ns ? 70 (except i 2 s mode) tbsd - 70 ns bclk ? ? to sdto ? 70 slave mode tlrb 50 - - ns exlrck edge to exbclk ? ? ( note 21 ) tblr 50 - - ns exbclk ? ? to exlrck edge ( note 21 ) tlrd - - 80 ns exlrck edge to sdto (msb) (except i 2 s mode) tbsd - - 80 ns exbclk ? ? to sdto note 19. msbs, bckp bits = ?00? or ?11? note 20. msbs, bckp bits = ?01? or ?10? note 21. exbclk rising edge must not occur at the same time as exlrck edge. ms0404-e-02 2007/08 - 10 - [ak5701] parameter symbol min typ max units control interface timing (csp pin = ?l?) cclk period tcck 142 - - ns cclk pulse width low tcckl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn ?h? time tcsw 150 - - ns tcss 50 - - ns csn edge to cclk ? ? ( note 22 ) tcsh 50 - - ns cclk ? ? to csn edge ( note 22 ) control interface timing (csp pin = ?h?) cclk period tcck 142 - - ns cclk pulse width low tcckl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn ?l? time tcsw 150 - - ns tcss 50 - - ns csn edge to cclk ? ? ( note 22 ) tcsh 50 - - ns cclk ? ? to csn edge ( note 22 ) power-down & reset timing pdn pulse width ( note 23 ) tpd 150 - - ns note 24 ) pmadl or pmadr ? ? to sdto valid ( hpf1-0 bits = ?00? tpdv - 3088 - 1/fs hpf1-0 bits = ?01? tpdv - 1552 - 1/fs hpf1-0 bits = ?10? tpdv - 784 - 1/fs note 22. cclk rising edge must not occur at the same time as csn edge. note 23. the ak5701 can be reset by the pdn pin = ?l?. note 24. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?. ms0404-e-02 2007/08 - 11 - [ak5701] timing diagram bclk 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd tbck tbckh tbckl 50%dvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 dmck = tmckl x fmck x 100 lrck 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 2. clock timing (pll/ext master mode) lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "0") (bckp = "1") figure 3. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?0?) ms0404-e-02 2007/08 - 12 - [ak5701] lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "1") (bckp = "0") figure 4. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?1?) lrck 50%dvdd bclk 50%dvdd sdto 50%dvdd tbsd tmblr tbckl tlrd figure 5. audio interface timing (pll/ex t master mode & except dsp mode) ms0404-e-02 2007/08 - 13 - [ak5701] 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "0") (bckp = "1") figure 6. clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mode; msbs = 0) 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "1") (bckp = "0") figure 7. clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mode; msbs = 1) ms0404-e-02 2007/08 - 14 - [ak5701] 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 8. clock timing (pll slave mode; pll reference clock = mcki pin & except dsp mode) exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "0") (bckp = "1") figure 9. audio interface timing (pll slave mode & dsp mode; msbs = 0) ms0404-e-02 2007/08 - 15 - [ak5701] exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "1") (bckp = "0") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = 1) 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 11. clock timing (ext slave mode) ms0404-e-02 2007/08 - 16 - [ak5701] exlrck vih vil tblr exbclk vih vil tlrd sdto 50%dvdd tlrb tbsd msb figure 12. audio interface timing (pll/ext slave mode) ms0404-e-02 2007/08 - 17 - [ak5701] csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 13. write command input timing (csp pin = ?l?) csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 14. write data input timing (csp pin = ?l?) ms0404-e-02 2007/08 - 18 - [ak5701] csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 15. write command input timing (csp pin = ?h?) csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 16. write data input timing (csp pin = ?h?) ms0404-e-02 2007/08 - 19 - [ak5701] pmadl bit or pmadr bit tpdv sdto 50%dvdd figure 17. power down & reset timing 1 tpd pdn vil figure 18. power down & reset timing 2 ms0404-e-02 2007/08 - 20 - [ak5701] operation overview system clock there are the following five clock modes to interface with external devices ( table 1 and table 2 ) mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 25 ) 1 1 see table 4 figure 19 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 20 pll slave mode 2 (pll reference clock: exlrck or exbclk pin) 1 0 see table 4 figure 21 ext slave mode 0 0 x figure 22 ext master mode ( note 26 ) 0 0 x figure 23 note 25. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from the mcko pin when mcko bit is ?1?. note 26. in case of ext master mode, the register should be set as figure 49 . table 1. clock mode setting (x: don?t care) bclk pin, lrck pin, mode mcko bit mcko pin mcki pin exbclk pin exlrck pin 0 l bclk pin selected by pll3-0 bits lrck pin pll master mode (selected by bcko1-0 bits) selected by ps1-0 bits (1fs) ( note 27 ) 1 0 l exbclk pin pll slave mode selected by pll3-0 bits exlrck pin selected by ps1-0 bits (pll reference clock: mcki pin) (1fs) ( t 32fs) 1 pll slave mode (pll reference clock: exlrck or exbclk pin) 0 l gnd exbclk pin exlrck pin (selected by pll3-0 bits) (1fs) exbclk pin selected by fs1-0 bits exlrck pin ext slave mode 0 l (1fs) ( t 32fs) bclk pin selected by fs1-0 bits lrck pin ext master mode 0 l (selected by bcko1-0 bits) (1fs) note 27. lrck becomes 2fs at pll master mode & dsp mode 1. table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak5701 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak5701 is slave mode. after exiting reset state, the ak5701 goes to master mode by changing m/s bit = ?1?. m/s bit mode used pins 0 slave mode exbclk, exlrck (default) 1 master mode bclk, lrck table 3. select master/salve mode ms0404-e-02 2007/08 - 21 - [ak5701] ms0404-e-02 2007/08 - 22 - pll mode when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4 , whenever the ak5701 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? o ?1?) or sampling frequency changes. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ : ] c[f] pll lock time (max) 0 0 0 0 0 exlrck pin 1fs 6.8k 220n 80ms 2 0 0 1 0 exbclk pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 exbclk pin 64fs 10k 4.7n 2ms 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 8 1 0 0 0 mcki pin 19.2mhz 10k 4.7n 40ms 9 1 0 0 1 mcki pin 12mhz ( note 28 ) 10k 4.7n 40ms (default) 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms 14 1 1 1 0 mcki pin 13mhz 10k 220n 60ms 15 1 1 1 1 mcki pin 26mhz 10k 220n 60ms others others n/a note 28. please see table 5 regarding the difference between pll3-0 bits = ?0110?(mode 6) and ?1001?(mode 9). table 4. setting of pll mode (*fs: sampling frequency) 2) setting of sampling frequency in pll mode when pll reference clock input is mcki pin, the sampli ng frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 7.349918khz ( note 29 ) 5 0 1 0 1 11.025khz 11.024877khz ( note 29 ) 6 0 1 1 0 14.7khz 14.69984khz ( note 29 ) 7 0 1 1 1 22.05khz 22.04975khz ( note 29 ) 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 29.39967khz ( note 29 ) 15 1 1 1 1 44.1khz 44.0995khz ( note 29 ) (default) others others n/a note 29. in case of pll3-0 bits = ?1001? table 5. setting of sampling frequency at pm pll bit = ?1? and reference clock=mcki pin [ak5701] when pll reference clock input is exlrck or exbclk pin, the sampling frequency is selected by fs3 and fs2 bits ( table 6 ). fs3 bit fs2 bit sampling frequency range mode fs1 bit fs0 bit 0 0 x x 7.35khz fs 12khz 0 0 1 x x 12khz < fs 24khz 1 2 1 x x x 24khz < fs 48khz (default ) others others n/a (x: don?t acre, n/a: not available) table 6. setting of sampling frequency at pmpll bit = ?1? and reference=exlrck/exbclk v pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bclk pins go to ?l? and irregul ar frequency clock is output from the mcko pin at mcko bit is ?1? before the pll goes to lo ck state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, the mcko pin changes to ?l? ( table 7 ). in dsp mode 0 and 1, bclk and lrck st art to output corresponding to lch data af ter pll goes to lock state by setting pmpll bit = ?0? ? ?1?. when msbs and bckp bits are ?01? or ?10? in dsp mode 0 and 1, bclk ?h? time of the first pulse becomes 1/(256fs) shorter than ?h? time except for the first pulse. when sampling frequency is changed, bclk and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state bclk pin lrck pin mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except above case) ?l? output invalid invalid invalid 1fs output ( pll lock ?l? output see table 9 see table 10 note 30 ) note 30. lrck becomes 2fs at dsp mode 1. table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. after that, the clock selected by table 9 is output from the mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocke d. for dac, the output signa l should be muted by writi ng ?0? to dacl, dach and dacs bits. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock (except above case) ?l? output invalid pll lock ?l? output see table 9 table 8. clock operation at pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) ms0404-e-02 2007/08 - 23 - [ak5701] pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz , 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz or 27mhz) is input to mcki pin, the mcko, bclk and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. the bclk output frequency is selected among 32fs or 64fs, by bcko1-0 bits ( table 10 ). ak5701 dsp or p p mcko bclk lrck sdto bclk lrck sdti mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz mclk figure 19. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bclk output frequency bcko1 bit bcko0 bit 0 0 n/a 0 1 32fs (default) 1 0 64fs 1 1 n/a table 10. bclk output frequency at master mode (n/a: not available) ms0404-e-02 2007/08 - 24 - [ak5701] pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, exbclk or exlrck pin. the required clock to the ak5701 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 4 ). a) pll reference clock: mcki pin exbclk and exlrck inputs should be synchronized with mcko output. the phase between mcko and exlrck is not important. the mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ). ak5701 dsp or p p mcko exbclk exlrck sdto bclk lrck sdti mcki 1fs t 32fs mclk 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz figure 20. pll slave mode 1 (pll reference clock: mcki pin) the external clocks (mcki, exbclk and exlrck) should always be present whenever the adc is in operation (pmadl bit = ?1? or pmadr bit = ?1?). if these clocks are not provided, the ak5701 may draw excess current and it is not possible to operate properly because u tilizes dynamic refreshed logic internally. if the external clocks are not present, the adc should be in the power-down mode (pmadl=pmadr bits = ?0?). b) pll reference clock: exbclk or exlrck pin table 6 ). sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits ( ak5701 dsp or p p mcki exbclk exlrck sdto bclk lrck sdti 1fs 32fs, 64fs figure 21. pll slave mode 2 (pll reference clock: exlrck or exbclk pin) ms0404-e-02 2007/08 - 25 - [ak5701] ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak5701 becomes ext mode. master clock is input from the mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), exlrck (fs) and exbclk ( t 32fs). the master clock (mcki) should be synchronized with exlrck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits ( table 11 ). mcki input frequency sampling frequency range mode fs3-2 bits fs1 bit fs0 bit 0 0 0 256fs x 7.35khz a 48khz x 0 1 1024fs 1 7.35khz a 13khz x 1 0 512fs 2 7.35khz a 26khz x 1 1 256fs 3 7.35khz a 48khz (default) table 11. mcki frequency at ext slave mode (p mpll bit = ?0?, m/s bit = ?0?) (x: don?t care) the external clocks (mcki, exbclk and exlrck) should always be present whenever the adc is in operation (pmadl bit = ?1? or pmadr bit = ?1?). if these clocks are not provided, the ak5701 may draw excess current and it is not possible to operate properly because u tilizes dynamic refreshed logic internally. if the external clocks are not present, the adc should be in the power-down mode (pmadl=pmadr bits = ?0?). ak5701 dsp or p p mcki exbclk exlrck sdto bclk lrck sdti mcko 1fs t 32fs mclk 256fs, 512fs or 1024fs figure 22. ext slave mode ms0404-e-02 2007/08 - 26 - [ak5701] ext master mode (pmpll bit = ?0?, m/s bit = ?1?, te3-0 bits = ?0101?, tmaster bit = ?1?) figure 49 the ak5701 becomes ext master mode by setting as . master clock is input from the mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 12 ). mcki input frequency sampling frequency range mode fs3-2 bits fs1 bit fs0 bit 0 0 0 256fs x 7.35khz a 48khz x 0 1 1024fs 1 7.35khz a 13khz x 1 0 512fs 2 7.35khz a 26khz x 1 1 256fs 3 7.35khz a 48khz (default) table 12. mcki frequency at ext master mode (x: don?t care) mcki should always be present whenever the adc is in operation (pmadl bit = ?1? or pmadr bit = ?1?). if mcki is not provided, the ak5701 may draw excess current and it is not possible to operate prope rly because utilizes dynamic refreshed logic internally. if mcki is not present, the adc should be in the power-down mode (pmadl=pmadr bits = ?0?). ak5701 dsp or p p mcki bclk lrck sdto bclk lrck sdti mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 23. ext master mode bclk output frequency bcko1 bit bcko0 bit 0 0 n/a 0 1 32fs (default) 1 0 64fs 1 1 n/a table 13. bclk output frequency at master mode (n/a: not available) ms0404-e-02 2007/08 - 27 - [ak5701] bypass mode when thr bit = ?1?, m/s bit = ?0?, pmadl bit = ?0? a nd pmadr bit = ?0?, input clocks and data of exlrck, exbclk and exsdti pins are bypassed to lrck, bclk and sdto pins, respectively. when thr bit = ?1?, m/s bit = ?0? and pmadl bit = ?1? or pmadr bit = ?1?, input clocks of exlrck and exbclk pins are bypassed to lrck and bclk pins, and adc data is output from the sdto pin. pmadl bit thr bit m/s bit bclk/lrck sdto mode figure pmadr bit 00 l l power down (default ) 0 01/10/11 l adc data slave mode 00 output l power down 0 1 01/10/11 output adc data master mode 00 exbclk/exlrck exsdti bypass mode figure 24 0 01/10/11 exbclk/exlrck adc data slave & bypass figure 25 00 n/a n/a n/a 1 1 01/10/11 output adc data master mode table 14. bypass mode select (n/a: not available) ak5701 dsp or p p bclk lrck sdti lrck sdto 1fs bclk t 32fs dsp or p p lrck sdto 1fs bclk t 32fs exbclk exlrck exsdti figure 24. bypass mode ak5701 dsp or p p bclk lrck sdti lrck sdto 1fs bclk t 32fs dsp or p p lrck analog in 1fs bclk t 32fs exbclk exlrck lin/rin figure 25. slave & bypass mode ms0404-e-02 2007/08 - 28 - [ak5701] audio interface format fore types of data format are available a nd are selected by setting the dif1-0 bits ( table 15 ). in all modes, the serial data is msb first, 2?s complement format. audio interface formats can be used in both master a nd slave modes, but dsp mode 1 supports pll master mode only. lrck, bclk and sdto pins are used in master mode. exlrck, exbclk and sdto pins are used in slave mode. in modes 2 a nd 3, the sdto is clocked out on the falling edge (? p ?) of bclk/exbclk. mode dif1 bit dif0 bit sdto bclk, exbclk figure 0 0 0 dsp mode 0 32fs see table 16 1 0 1 dsp mode 1 t 32fs 2 1 0 msb justified t 32fs figure 34 i 2 s compatible 3 1 1 t 32fs figure 35 (default) table 15. audio interface format in modes 0 and 1 (dsp mode 0 and 1), the audio i/f timing is changed by bckp and msbs bits. when bckp bit is ?0?, sdto data is output by rising edge (? n ?) of bclk/exbclk. when bckp bit is ?1?, sdto data is output by falling edge (? p ?) of bclk/exbclk. msb data position of sdto can be shifted by msbs bit. the shifted period is a half of bclk/exbclk. dif1 dif0 msbs bckp audio interface format 0 0 msb of sdto is output by the rising edge (? n ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 26 ). 0 1 msb of sdto is output by the falling edge (? p ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 27 ). 1 0 msb of sdto is output by next rising edge (? n ?) of the falling edge (? p ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 28 ). 0 0 1 1 msb of sdto is output by next falling edge (? p ?) of the rising edge (? n ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 29 ). 0 0 msb of sdto is output by the rising edge (? n ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 30 ). 0 1 msb of sdto is output by the falling edge (? p ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 31 ). 1 0 msb of sdto is output by next rising edge (? n ?) of the falling edge (? p ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 32 ). 0 1 1 1 msb of sdto is output by next falling edge (? p ?) of the rising edge (? n ?) of the first bclk/exbclk after the rising edge (? n ?) of lrck/exlrck ( figure 33 ). (default) table 16. audio interface format in mode 0, 1 if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? 1? at 16bit data is converted to ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? 1? at 8-bit data will be converted to ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data. ms0404-e-02 2007/08 - 29 - [ak5701] exlrck lrck 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 lch lch rch rch exbclk(32fs) bclk(32fs) sdto ( o ) figure 26. mode 0 timing (bckp = ?0?, msbs = ?0?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) figure 27. mode 0 timing (bckp = ?1?, msbs = ?0?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) figure 28. mode 0 timing (bckp = ?0?, msbs = ?1?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) figure 29. mode 0 timing (bckp = ?1?, msbs = ?1?, m/s = ?0? or ?1?) ms0404-e-02 2007/08 - 30 - [ak5701] lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 8 87 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 15 figure 30. mode 1 timing (bckp = ?0?, msbs = ?0?, m/s = ?1?) lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 8 87 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 15 figure 31. mode 1 timing (bckp = ?1?, msbs = ?0?, m/s = ?1?) lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 8 87 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 15 figure 32. mode 1 timing (bckp = ?0?, msbs = ?1?, m/s = ?1?) lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 8 87 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 15 figure 33. mode 1 timing (bckp = ?1?, msbs = ?1?, m/s = ?1?) ms0404-e-02 2007/08 - 31 - [ak5701] 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 32 11 14 1 5 15 14 4 876 0 3 2 1 5 14 11 15 13 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 21 15 15:msb, 0:lsb lch data rch data 2 1 13 16 0 16 3 13 3 13 13 3 exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) exbclk(64fs) bclk(64fs) sdto ( o ) figure 34. mode 2 timing (msb justified, m/s = ?0? or ?1?) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 0 1 15 5 13 7 7 1 43 11 14 2 6 0 15 5 13 7 7 1 4 3 2 6 14 11 0 13 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 15 13 2 1 15:msb, 0:lsb lch data rch data 2 1 14 16 0 16 3 14 14 3 2 14 3 4 exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) exbclk(64fs) bclk(64fs) sdto ( o ) figure 35. mode 3 timing (i 2 s, m/s = ?0? or ?1?) pmadl, pmadr and mix bits select mono or stereo mode of adc output data. alc operation (alc bit = ?1?) or digital volume operation (alc bit = ?0?) is applied to the data in table 17 . pmadl bit pmadr bit mix bit adc lch data adc rch data 0 0 x all ?0? all ?0? (default) 0 1 x rch input signal rch input signal 1 0 x lch input signal lch input signal 0 lch input signal rch input signal 1 1 1 (l+r)/2 (l+r)/2 table 17. mono/stereo selection (x: don?t care) ms0404-e-02 2007/08 - 32 - [ak5701] digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is selected by hpf1-0 bits ( table 18 ) and scales with sampling rate (fs). the default value is 3.4hz (@fs=44.1khz). fc hpf1 bit hpf0 bit fs=44.1khz fs=22.05khz fs=11.025khz 0 0 3.4hz 1.7hz 0.85hz (default) 0 1 6.8hz 3.4hz 1.7hz 1 0 13.6hz 6.8hz 3.4hz 1 1 n/a n/a n/a table 18. digital hpf cut-off frequency (n/a: not available) mic/line input selector the ak5701 has input selector. when mdif1 and mdif2 bits are ?0?, inl and inr bits select lin1/lin2 and rin1/rin2, respectively. when mdif1 a nd mdif2 bits are ?1?, lin1, rin1, lin2 and rin2 pins become lin+, lin , rin and rin+ pins respectively. in this case, full-differential input is available ( figure 37 ). mdif1 bit mdif2 bit inl bit inr bit lch rch 0 lin1 rin1 (default) 0 1 lin1 rin2 0 lin2 rin1 0 1 1 lin2 rin2 0 0 x lin1 rin+/ 1 1 x n/a n/a 0 n/a n/a 0 x 1 rin2 lin+/ 1 1 x x lin+/ rin+/ table 19. mic/line in path select (n/a: not available) lin1/lin+ pin a dc lch rin1/ lin pi n inl bit mdif1 bit rin2/ rin+ pin a dc rch lin2/ rin pi n inr bit mdif2 bit ak5701 figure 36. mic/line input selector ms0404-e-02 2007/08 - 33 - [ak5701] in1 ? pin in1+ pin mpwr pin ak5701 mic-amp 1k 1k figure 37. connection example for full-differential mic input (mdif1/2 bits = ?1?) v mic gain amplifier the ak5701 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain1-0 bits ( table 20 ). the typical input impedance is 60k (typ)@mgain1-0 bits = ?00? or 30k (typ)@mgain1-0 bits = ?01? or ?10?. mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +15db (default) 1 0 +30db 1 1 n/a table 20. mic input gain (n/a: not available) v mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.75 x avdd and the load resistance is minimum 0.5k . in case of using two sets of stereo mic, the load resistance is minimum 2k for each channel. any capacitor must not be connected directly to the mpwr pin ( figure 38 ). pmmp bit mpwr pin 0 hi-z (default) 1 output table 21. mic power mpwr pin 2k mic power microphone lin1 pin microphone rin1 pin microphone lin2 pin microphone rin2 pin 2k 2k 2k figure 38. mic block circuit ms0404-e-02 2007/08 - 34 - [ak5701] alc operation the alc (automatic level control) is done by alc block when alc bit is ?1?. 1. alc limiter operation during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level ( table 22 ), the ivl and ivr values (same value) are attenuated automatically by the amount defined by the alc limiter att step ( table 23 ). when zelmn bit = ?0? (zero cross detec tion is enabled), the ivl and ivr valu es are changed by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both alc lim iter and recovery operation ( table 24 ). when zelmn bit = ?1? (zero cross detection is disabled), ivl and ivr values are immediately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. the attenuation operation is executed c ontinuously until the input signal level becomes alc limiter detection level ( table 22 ) or less. after completing the attenuation operation, unl ess alc bit is changed to ?0?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output t 2.5dbfs 2.5dbfs > alc output t 4.1dbfs (default) 0 1 alc output t 4.1dbfs 4.1dbfs > alc output t 6.0dbfs 1 0 alc output t 6.0dbfs 6.0dbfs > alc output t 8.5dbfs 1 1 alc output t 8.5dbfs 8.5dbfs > alc output t 12dbfs table 22. alc limiter detection leve l / recovery counter reset level zelmn lmat1 lmat0 alc limiter att step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 4 step 1.500db 0 1 1 8 step 3.000db 1 x x 1step 0.375db table 23. alc limiter att step zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 24. alc zero crossing timeout period ms0404-e-02 2007/08 - 35 - [ak5701] 2. alc recovery operation the alc recovery operation waits for the wtm1-0 bits ( table 25 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 22 ) during the wait time, the alc recovery operation is executed. the ivl and ivr values are automatically incremen ted by rgain1-0 bits ( table 26 ) up to the set reference level ( table 27 ) with zero crossing detection which is timeout period set by ztm1-0 bits ( table 24 ). then the ivl and ivr are set to the same value for both channels. the alc recove ry operation is executed at a period set by wtm1-0 bits. if ztm1-0 is longer than wtm1-0 and no zero crossing occurs, the alc recovery operation is executed at a period set by ztm1-0 bits. for example, when the current ivol value is 30h and rgain1 -0 bits are set to ?01?, ivol is changed to 32h by the auto limiter operation and then the input signal level is ga ined by 0.75db (=0.375db x 2). when the ivol value exceeds the reference level (ref7-0), the ivol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when larg e noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. alc recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 25. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 26. alc recovery gain step ref7-0 gain(db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 0.375db : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 00h mute table 27. reference level at alc recovery operation ms0404-e-02 2007/08 - 36 - [ak5701] 3. example of alc operation table 28 shows the examples of the alc setting for mic recording. fs=8khz fs=44.1khz register name comment data operation data operation lmth limiter detection level 01 01 ? 4.1dbfs ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 10 11.6ms recovery waiting period wtm1-0 *wtm1-0 bits should be the same data as ztm1-0 bits 00 16ms 10 11.6ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0, gain of ivol 91h 0db 91h 0db ivr7-0 lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step alc alc enable 1 enable 1 enable table 28. example of the alc setting the following registers should not be changed during the al c operation. these bits should be changed after the alc operation is finished by alc bit = ?0? or pmadl=pmadr bits = ?0?. ? lmth, lmat1-0, wtm1-0, ztm1-0, rgain1-0, ref7-0, zelmn manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm1-0) wr (ref7-0) wr (ivl/r7-0) wr (lmat1-0, rgain1-0, zelmn, lmth1-0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=18h&19h, data=91h (2) addr=1ah, data=00h (3) addr=1bh, data=e1h alc operation (4) addr=1ch, data=81h note : wr : write figure 39. registers set-up sequence at alc operation ms0404-e-02 2007/08 - 37 - [ak5701] input digital volume (manual mode) the input digital volume becomes a manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc operation (ztm1-0, lmth and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. table 29 ivl7-0 and ivr7-0 bits set the gain of the volume control ( ). the ivol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. if ivl7-0 or ivr7-0 bits are written during pmadl=pmadr b its = ?0?, ivol operation starts with the written values at the end of the adc initialization cycle after pmadl or pmadr bit is changed to ?1?. ivl7-0 gain (db) step ivr7-0 f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h 0.375 0.375db : : 03h 53.25 02h 53.625 01h 54 00h mute table 29. input digital volume setting ms0404-e-02 2007/08 - 38 - [ak5701] when writing to the ivl7-0 and ivr7-0 b its continuouslly, the control register shoul d be written in an interval more than zero crossing timeout. if not, ivl and ivr are not changed since zero crossing counter is reset at every write operation. if the same register value as the previous write operation is wr itten to ivl and ivr, this write operation is ignored and zero crossing counter is not reset. therefore, ivl and ivr can be written in an interval le ss than zero crossing timeout. a lc bit a lc status disable enable disable ivl7-0 bits e1h(+30db) ivr7-0 bits c6h(+20db) internal ivl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) internal ivr c6h(+20db) e1(+30db) --> f1(+36db) c6h(+20db) (1) (2 ) figure 40. ivol value during alc operation (1) the ivl value becomes the st art value if the ivl and ivr are different when the alc starts. the wait time from alc bit = ?1? to alc operation start by ivl7-0 bits is at most recovery time (wtm1-0 bits) plus zerocross timeout period (ztm1-0 bits). (2) writing to ivl and ivr registers (18h and 19h) is ignored during alc operation. after alc is disabled, the ivol changes to the last written data by zero crossing or timeout. when alc is enabled again, alc bit should be set to ?1? by an interval more than zero crossi ng timeout period after alc bit = ?0?. system reset when power-up, the ak5701 should be reset by bringing the pdn pi n = ?l?. this ensures that all internal registers reset to their initial values. the adc enters an initialization cycle that starts when the pmadl or pmadr bit is changed from ?0? to ?1?. the initialization cycle time is 3088/fs=70.0ms@fs =44.1khz when hpf1-0 bits are ?00? ( table 30 ). during the initialization cycle, the adc digital data outputs of both channels are fo rced to a 2?s compliment, ?0 ?. the adc output reflects the analog input signal after the in itialization cycle is complete. init cycle hpf1 bit hpf0 bit cycle fs=44.1khz fs=22.05khz fs=11.025khz 0 0 3088/fs 70.0ms (recommendation) 140.0ms 280.1ms (default ) 0 1 1552/fs 35.2ms 70.4ms 140.8ms (recommendation) 1 0 784/fs 17.8ms 35.6ms 71.1ms (recommendation) 1 1 n/a n/a n/a n/a table 30. adc initialization cycle (n/a: not available) ms0404-e-02 2007/08 - 39 - [ak5701] serial control interface internal registers may be written by us ing the 3-wire p interface pins (csn, cclk and cdti). the csp pin selects the polarity of the csn pin and chip address. 1) csp pin = ?l? the data on this interface consists of a 2-bit chip address (fixed to ?10?), read/write (fixed to ?1?), register address (msb first, 5bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? n ?) of cclk. address and data are latched on the 16th cclk rising edge (? n ?) after csn falling edge(? p ?). csn should be set to ?h? once after 16 cclks for each address. clock speed of cclk is 7mhz (max ). the value of internal re gisters are initialized by the pdn pin = ?l?. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1-c0: chip address (c1 = ?1?, c0 = cad0) ; fixed to ?10? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a4-a0: register address d7-d0: control data clock, ?h? or ?l? ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? figure 41. serial control i/f timing (csp pin = ?l?) 2) csp pin = ?h? the data on this interface consists of a 2-bit chip address (fixed to ?01?), read/write (fixed to ?1?), register address (msb first, 5bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? n ?) of cclk. address and data are latched on the 16th cclk rising edge (? n ?) after csn rising edge(? n ?). csn should be set to ?l? once after 16 cclks for each address. clock speed of cclk is 7mhz (max ). the value of internal re gisters are initialized by the pdn pin = ?l?. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1-c0: chip address (c1 = ?0?, c0 = cad1) ; fixed to ?01? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a4-a0: register address d7-d0: control data clock, ?h? or ?l? ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? figure 42. serial control i/f timing (csp pin = ?h?) ms0404-e-02 2007/08 - 40 - [ak5701] register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm pmadr pmadl 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmpll 12h signal select 0 0 0 pmmp mdif2 mdif1 inr inl 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 14h audio format select 0 0 1 mix msbs bckp dif1 dif0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 16h clock output select 0 0 0 0 thr mcko ps1 ps0 17h volume control 0 0 0 0 0 0 0 ivolc 18h lch input volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 19h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 1bh alc mode control 1 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 1ch alc mode control 2 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 1eh mode control 2 0 0 0 0 0 0 0 tmaster note 31. pdn pin = ?l? resets the registers to their default values. note 32. ?0? must be sent to the register written as ?0? and ?1? must be sent to the register written as ?1?. for addresses except for 10h to 1eh, data must not be written. ms0404-e-02 2007/08 - 41 - [ak5701] register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm pmadr pmadl default 0 0 0 0 0 0 0 0 pmadl: mic-amp lch and adc lch power management 0: power down (default) 1: power up pmadr: mic-amp rch and adc rch power management 0: power down (default) 1: power up when the pmadl or pmadr bit is changed from ?0? to ?1?, the initialization cycle (3088/fs=70.0ms@fs= 44.1khz, hpf1-0 bits = ?00?) starts. after initializing, digital data of the adc is output. pmvcm: vcom power management 0: power down (default) 1: power up when any blocks are powered-up, th e pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when pmadl=pmadr=pmpll=pmmp=mcko bits = ?0?. each block can be powered-down respectivel y by writing ?0? in each bit of this a ddress. when the pdn pin is ?l?, all blocks are powered-down regardless as setting of this address. in this case, register is initialized to the default value. when pmvcm, pmadl, pmadr, pmpll and mcko bits are ?0?, all blocks are powered-down. the register values remain unchanged. power supply current is 20 p a(typ) in this case. for fully shut down (typ. 1 p a), the pdn pin should be ?l?. when the adc is not used, external clocks may not be pres ent. when adc is used, external clocks must always be present. addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmpll default 0 0 1 0 0 1 0 0 pmpll: pll power management 0: ext mode and power down (default) 1: pll mode and power up m/s: master / slave mode select 0: slave mode (default) 1: master mode pll3-0: pll reference clock select ( table 4 ) default: ?1001?(mcki pin=12mhz) ms0404-e-02 2007/08 - 42 - [ak5701] addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h signal select 0 0 0 pmmp mdif2 mdif1 inr inl default 0 0 0 0 0 0 0 0 inl: adc lch input source select 0: lin1 pin (default) 1: lin2 pin inr: adc rch input source select 0: rin1 pin (default) 1: rin2 pin mdif1: adc lch input type select 0: single-ended input (lin1/lin2 pin: default) 1: full-differential input (lin+/lin ? pin) mdif2: adc rch input type select 0: single-ended input (rin1/rin2 pin: default) 1: full-differential input (rin+/rin ? pin) pmmp: mpwr pin power management 0: power down: hi-z (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 default 0 0 0 0 0 0 0 1 table 20 ) mgain1-0: mic-amp gain control ( default: ?01?(+15db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h audio format select 0 0 1 mix msbs bckp dif1 dif0 default 0 0 1 0 0 0 1 1 table 15 ) dif1-0: audio interface format ( default: ?11? (i 2 s) bckp: bclk/exbclk polarity at dsp mode ( table 16 ) ?0?: sdto is output by the rising edge (? ?) of bclk/exbclk. (default) ?1?: sdto is output by the falling edge (? ?) of bclk/exbclk. msbs: lrck/exlrck polarity at dsp mode ( table 16 ) ?0?: the rising edge (? ?) of lrck/exlrck is half clock of bclk/exbclk before the channel change. (default) ?1?: the rising edge (? ?) of lrck/exlrck is one clock of bclk/exbclk before the channel change. mix: adc output data select ( table 17 ) ?0?: normal operation (default) ?1?: (l+r)/2 ms0404-e-02 2007/08 - 43 - [ak5701] addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 default 0 0 0 1 1 1 1 1 table 5 and table 6 ) and mcki frequency select ( table 11 ) fs3-0: sampling frequency select ( default: ?1111? (44.1khz) fs3-0 bits select sampling frequency at p ll mode and mcki frequency at ext mode. bcko1-0: bclk output frequency select at master mode ( table 10 ) default: ?01? (32fs) hpf1-0: offset cancel hpf cut-off frequency and adc initialization cycle ( table 18 , table 30 ) default: ?00? (fc=3.4hz@fs= 44.1khz, init cycle=3088/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h clock output select 0 0 0 0 thr mcko ps1 ps0 default 0 0 0 0 0 0 0 0 table 9 ) ps1-0: mcko output frequency select ( default: ?00?(256fs) mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. table 14 ) thr: bypass mode ( 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 17h volume control 0 0 0 0 0 0 0 ivolc default 0 0 0 0 0 0 0 1 ivolc: input digital volume control mode select 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume level, while register values of ivl7-0 bits are not written to ivr7-0 bits. when ivolc bit = ?0?, ivl7-0 bits control lch level and ivr7-0 bits control rch level, respectively. addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h lch input volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 19h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 default 1 0 0 1 0 0 0 1 ivl7-0, ivr7-0: input digital volume; 0.375db step, 242 level ( table 29 ) default: ?91h? (0db) ms0404-e-02 2007/08 - 44 - [ak5701] addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 default 0 0 0 0 0 0 0 0 wtm1-0: alc recovery waiting period ( table 25 ) default: ?00? (128/fs) ztm1-0: alc limiter/recovery operation zero crossing timeout period ( table 24 ) default: ?00? (128/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1bh alc mode control 1 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery operation. 0.375db step, 242 level ( table 27 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch alc mode control 2 alc zelmn lmat1 lmat0 lmth1 lmth0 rgain1 rgain0 default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 22 ) default: ?00? table 26 ) rgain1-0: alc recovery gain step ( default: ?00? lmat1-0: alc limiter att step ( table 23 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable ms0404-e-02 2007/08 - 45 - [ak5701] addr register name d7 d6 d5 d4 d3 d2 d1 d0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 default 1 0 1 0 0 0 0 0 te3-0: ext master mode enable when te3-0 bits is set to ?0101?, the write operation to addr=1eh is enabled. te3-0 bits should be set to ?1010? except for ext master mode. te3-0 bits must not be set to the value except for ?1010? and ?0101?. default: ?1010? addr register name d7 d6 d5 d4 d3 d2 d1 d0 1eh mode control 2 0 0 0 0 0 0 0 tmaster default 0 0 0 0 0 0 0 0 tmaster: ext master mode the write operation to tmaster bit is enabled when te3-0 bits = ?0101?. 0: except ext master mode (default) 1: ext master mode ms0404-e-02 2007/08 - 46 - [ak5701] system design figure 43 and figure 44 shows the system connection diagram for the ak5701. the evaluation board [akd5701] demonstrates the optimum layout, power supply arrangements and measurement results. mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck a k5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 2.2k 2.2k 2.2k 2.2k external mic internal mic 0.1u 2.2u 0.1u power supply 2.4 3.6v dsp p rp analog ground digital ground 0.1u 10u 10u power supply 1.6 3.6v cp 0.1 x cp (note) dsp 1u 1u 1u 1u notes: - avss and dvss of the ak5701 should be distributed separately from the ground of external controllers. - all digital input pins should not be left floating. - when the ak5701 is ext mode (pmpll bit = ?0?), a resistor and capacitor of the vcoc pin is not needed. - when the ak5701 is pll mode (pmpll bit = ?1?), a resistor and capacitor of the vcoc pin is shown in table 4 . 0.1 x cp in parallel with cp+rp improves pll jitter characteristics. - mic input ac coupling capacitor should be 1 f or less to start the recording within 100ms. figure 43. typical connection diagram (mic input) ms0404-e-02 2007/08 - 47 - [ak5701] mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck a k5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 line in 0.1u 2.2u 0.1u power supply 2.4 3.6v dsp p rp analog ground digital ground 0.1u 10u 10u power supply 1.6 3.6v cp 0.1 x cp (note) dsp notes: - avss and dvss of the ak5701 should be distributed separately from the ground of external controllers. - all digital input pins should not be left floating. - when the ak5701 is ext mode (pmpll bit = ?0?), a resistor and capacitor of the vcoc pin is not needed. - when the ak5701 is pll mode (pmpll bit = ?1?), a resistor and capacitor of the vcoc pin is shown in table 4 . 0.1 x cp in parallel with cp+rp improves pll jitter characteristics. figure 44. typical connection diagram (line input) ms0404-e-02 2007/08 - 48 - [ak5701] 1. grounding and power supply decoupling the ak5701 requires careful attention to power suppl y and grounding arrangements. avdd and dvdd are usually supplied from the system?s analog supply. if avdd and dvdd ar e supplied separately, the power-up sequence is not critical. avss and dvss of the ak5701 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak5701 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak5701. 3. analog inputs the analog inputs are single-ended or full-differential and input resistance is 60k (typ)@mgain1-0 bits = ?00?, 30k (typ)@mgain1-0 bits = ?01? or ?10?. the input signal range scales with 0.6 x avdd vpp(typ)@mgain 1-0 bits = ?00? centered around the internal common voltage (0.5 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = 1/(2 rc). the adc output data format is 2?s complement. the dc offset including the adc?s own dc offset is removed by the internal hpf (fc=3.4hz@ hpf1-0 bits = ?00?, fs=44.1khz). the ak5701 can accept input voltages from avss to avdd at single-ended. ms0404-e-02 2007/08 - 49 - [ak5701] control sequence clock set up when adc is powered-up, the clocks must be supplied. 1. pll master mode. bclk pin lrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input m/s bit (addr:11h, d1) mcko pin output (8) (7) 40msec(max) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:12h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:13h mcko, bclk and lrck output figure 45. clock set up sequence (1) [ak5701] 2. pll slave mode (exlrck or exbclk pin) 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14h, data:23h addr:15h, data:2fh (4) addr:11h, data:0dh pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input figure 46. clock set up sequence (2) [ak5701] 3. pll slave mode (mcki pin) exbclk pin exlrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:10h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:11h mcko output start exbclk and exlrck input start figure 47. clock set up sequence (3) [ak5701] 4. ext slave mode example: audio i/f format: i2s input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:00h addr:14h, data:23h addr:15h, data:2fh mcki, exbclk and exlrck input (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) input (4) mcki pin input figure 48. clock set up sequence (4) [ak5701] 5. ext master mode te3-0 bits (addr:1dh, d7-4) "0101" (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin input m/s bit (addr:11h, d1) bclk pin lrck pin output tmaster bit (addr:1eh, d1) "1010" example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select: 256fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:26h addr:14h, data:23h addr:15h, data:2fh addr:1dh, data:50h addr:1eh, data:02h bclk and lrck output figure 49. clock set up sequence (5) [ak5701] 6. slave & bypass mode 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14h, data:23h addr:15h, data:2fh addr:16h, data:08h (4) addr:11h, data:0dh pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input figure 50. clock set up sequence (6) [ak5701] 7. bypass mode (1) power supply & pdn pin = ?l? ? ?h? (2) addr:16h, data:08h mcki, exbclk and exlrck input (1) power supply pdn pin thr bit (addr:16h, d3) (2) exlrck pin exbclk pin exsdti pin (3) input figure 51. clock set up sequence (7) [ak5701] ? mic input recording (stereo) fs3-0 bits (addr:15h, d3-0) mic control (addr:12h, d4 & addr:13h, d1-0) pmadl/r bit (addr:10h, d1-0) adc internal state 1111 x,xxx 0, 01 1, 01 power down initialize normal state power down 3088 / fs (1) (2) (6) alc state alc enable alc disable alc disable timer control (addr:1ah) xxh 0ah (3) alc control 1 (addr:1bh) xxh e1h (4) (7) (5) alc control 2 (addr:1ch) xxh 81h 01h (8) example: pll master mode audio i/f format:i2s sampling frequency:44.1khz pre mic amp:+15db mic power on alc setting:refer to figrure 37 alc bit = ?1? (2) addr:12h, data:10h addr:13h, data:01h (3) addr:1ah, data:0ah (1) addr:15h, data:2fh (4) addr:1bh, data:e1h (6) addr:10h, data:07h recording (7) addr:10h, data:04h (5) addr:1ch, data:81h (8) addr:1ch, data:01h figure 52. mic input recording sequence [ak5701] stop of clock master clock can be stopped when adc is not used. 1. pll master mode external mcki pmpll bit (addr:11h, d0) mcko bit (addr:16h, d2) input (3) (1) (2) "h" or "l" m/s bit (addr:11h, d1) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 44.1khz (2) addr:16h, data:00h (1) addr:11h, data:10h (3) stop an external mcki figure 53. clock stopping sequence (1) [ak5701] 3. pll slave mode (mcki pin) example audio i/f format: i2s pll reference clock: mcki= 11.2896mhz exbclk frequency: 64fs sampling frequency: 44.1khz (1) addr:11h, data:10h (3) stop the external clocks (2) addr:16h, data:00h external mcki pmpll bit (addr:11h, d0) input (1) (3) mcko bit (addr:16h, d2) (2) figure 55. clock stopping sequence (3) [ak5701] power down power supply current is typ. 20 p a by stopping clocks and setti ng pmvcm bit = ?0? after all blocks except for vcom are powered-down. power supply current can be shut down (typ. 1 p a) by stopping cloc ks and setting the pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized. ms0404-e-02 2007/08 - 60 - [ak5701] package 24pin qfn (unit: mm) 2.4 0.15 0.5 0.23 0.05 0.2 0.75 0.05 2.4 0.15 1 7 12 19 4.0 0.1 4.0 0.1 0.40 0.1 a b 0.10 m 0.08 6 24 13 18 pin #1 id (0.35 x 45 ) exposed pad note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate ms0404-e-02 2007/08 - 61 - [ak5701] marking ak5701vn 5701 x xxx 1 xxxx : date code identifier (4 digits) AK5701KN 5701k x xxx 1 xxxx : date code identifier (4 digits) ms0404-e-02 2007/08 - 62 - [ak5701] revision history date (yy/mm/dd) revision reason page contents 05/08/04 00 first edition 05/11/22 01 error correction 8 switching characteristics (pll slave mode) tbckl(min): 240ns ? 0.4 x tbck tbckh(min): 240ns ? 0.4 x tbck 25 pll slave mode a) mode 1: exbclk or exlrck ? mcki b) mode 2: mcki ? exbclk or exlrck 35 alc operation the sentence of ?the ivl and ivr are then set to the same value for both channels.? was deleted. 57 control sequence (mic recording) figure 51 (7) data=01h ? 04h (2) 72h&73h ? 12h&13h (3) 7ah ? 1ah (4) 7bh ? 1bh (5) 7ch ? 1ch 07/08/30 02 product addition 1, 3, 5, AK5701KN was added. 62 (1) ambient temperature ak5701vn : 30 a +85 q c AK5701KN : 40 a +85 q c (2) marking ak5701vn : ?5701? AK5701KN : ?5701k? spec addition 11 1. control interface timing(csp pin = ?l?) (1) csn ? p ? to cclk ? n ? csn edge to cclk ? n ? (2) cclk ? n ? to csn ? n ? cclk ? n ? to csn edge 2. control interface timing(csp pin = ?h?) (1) csn ? n ? to cclk ? n ? csn edge to cclk ? n ? (2) cclk ? n ? to csn ? p ? cclk ? n ? to csn edge 3. note 22 was added. error correction 30 figure 26 a figure 29 : ectbclk(32fs)/bclk(32fs) no of 1 st bit in fugure 15 31 31 figure 30 a figure 33 : bclk(64fs) no of 1 st bit in fugure : 15 31 spec addition 40 serial control i/f 1. csp pin = ?l? ?csn should be set to ?h? once after 16 cclks for each address.? was added. 2. csp pin = ?h? ?csn should be set to ?l? once after 16 cclks for each address.? was added. ms0404-e-02 2007/08 - 63 - [ak5701] important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. ms0404-e-02 2007/08 - 64 - |
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